Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the dielectric structure 106.
A drain bit line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate or p-well 103 toward a left sidewall of the floating gate structure 104 in FIG. 1. A source bit line junction 114 that is doped with the junction dopant is formed within the active device area 112 of the semiconductor substrate or p-well 103 toward a right sidewall of the floating gate structure 104 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology.
For example, during programming of the flash memory cell 100 that is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100. Alternatively, during erasing of the N-channel flash memory cell 100, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 120 coupled to the control gate structure 108, a drain terminal 122 coupled to the drain bit line junction 110, a source terminal 124 coupled to the source bit line junction 114, and a substrate or p-well terminal 126 coupled to the substrate or p-well 103. FIG. 3 illustrates an electrically erasable and programmable memory device 130 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 130 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2.
The array of flash memory cells 130 of FIG. 3 is illustrated with two columns and two rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to FIG. 3, in the array of flash memory cells 130 comprising an electrically erasable and programmable memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 132, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 134.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 136, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 138. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 130 are coupled together to a source voltage VSS, and the substrate or p-well terminal of all flash memory cells of the array 130 are coupled together to a substrate voltage VSUB.
FIG. 4 illustrates an example address generator 150 for cycling through addresses of an array of flash memory cells 152 of FIG. 5. The array of flash memory cells 152 for example is a sixteen Megabit memory device that is horizontally partitioned into thirty-two sectors, S0, S1, and so on to S31. Each of such sectors has five hundred and twelve rows of flash memory cells, and each row has a corresponding word line R0, R1, and so on to R511, that is each coupled to the control gate of all flash memory cells in a row.
In addition, the array of flash cells 152 is vertically partitioned into eight I/O areas I/O(0), I/O(1), and so on to I/O(7). Each of such I/O areas has one hundred and twenty eight columns of flash memory cells, and each column has a corresponding bit line C0, C1, and so on to C127, that is each coupled to the drain bit line junction of all flash memory cells in a column. Each of the eight I/O areas is coupled to a corresponding I/O of the flash memory device having the array of flash memory cells 152.
The address generator 150 generates twenty-one bits A[20:0] for specifying an address of eight flash memory cells to be accessed via the eight I/O's of the flash memory device. The address generator 150 includes a sector address generator that generates a 5-bit sector address A[20,16] for specifying one of the thirty-two sectors S0, S1, and so on to S31 to be selected. The address generator 150 also includes a row address generator 156 that generates a 9-bit row address A[15:7] for specifying one of the five hundred and twelve rows within the selected sector. The address generator 150 further includes a column address generator 158 that generates a 7-bit column address A[6:0] for specifying one of the hundred and twenty eight columns within each of the eight I/O areas.
During manufacture of the flash memory device comprised of the array of flash memory cells 152, such a flash memory device is tested for proper functionality by cycling through each of the addresses of the flash memory device. During such testing, the address generator 150 cycles through each of the addresses of the flash memory device. In addition, testing voltages are applied on flash memory cells comprising an address as specified by the address generator 150. Typically, the address generator increments by one-bit in a binary sequence through each of the addresses of the flash memory device.
Ideally, a flash memory device is tested for determining the operability of the flash memory device and of the array of flash memory cells 152 in particular. Any deleterious effect on the results of such testing from faulty characteristics of the test system such as from electrical characteristics of the address generator 150 for example is undesirable. If a flash memory cell of the array 152 fails from such electrical characteristics of the address generator 150, it is unclear whether the flash memory cell failed from faulty characteristics of the flash memory cell itself or from faulty characteristics of the test system.